David Greenlaw is VP of Product Engineering at Nvidia, responsible for the bring-up and production of silicon, boards and systems. Externally, David works with foundry and advanced component suppliers to ensure on-time, high quality products for commercial, automotive and high-performance computing applications.

David has worked on leading edge processors for 25 years, leading many different types of technical teams to success despite barriers related to language, culture, and badge color. He holds master’s degrees in EE from Stanford University and in physics from UT Austin.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She is a member of SEMI, SMTA, IMAPS, and MEPTEC. She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018. She is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

Design, Diagnosis, and Digitization for efficient system test and analytics to accelerate time to quality across the End to End Value Chain

The Networking Systems trend continues to push the boundaries on heterogeneous integrations of multiple dies in a package, silicon and photonics convergence, and higher density component integration on the system board. The need to detect known good die under any conditions at the earliest possible test step is key. A die will go through many test steps from its initial wafer test to use in its final application, presenting many opportunities for the known good die to become a known bad die, as electrical, thermal, power, signal integrity and test conditions change from one step to the next.

The use of advanced Si technology nodes brings in lower supply voltages and higher sensitivity to noise, and the use of advanced packaging increases design thermal sensitivity. These trends result in increases in:

• cost to “build in” reliability, voltage and thermal margins;
• higher functional complexity;
• noise/thermal driven
  interdependence of components on the board,
• more complex failure mechanisms that are harder to partition unless component level DFT and testing is carefully thought out in advance and designed in.

The key to address the challenges above, is to extend high coverage test, characterization and fault isolation methodology that serves the component eco-system to system community and enables tighter component to system co-optimization. The ability of any known bad die to dump out pertinent, actionable, digitized information at any point of fail end to end, that is traceable by a unique identifier, enables a proliferation of data analytics to be done, that can help to drive test coverage earlier in the supply chain, and lead to real-time root cause, quicker corrective action and cost reduction.

In the presentation we will cover differences between component level test and system level test and various paths to cover the gap. We will also show how test data is integrated to partition the failure and to feed into process control of direct suppliers and deeper into supply chain.

Yuri Bio:
Yuri Mitnick is component engineer in Cisco Systems, where he focuses on ASIC quality, reliability and product engineering. Prior to Cisco, he held positions at Intel, PDF Solutions, Qualcomm, where he led cross functional teams to support product life cycle requirements from R&D to volume production, including DFX activities, ramp up of characterization and test infrastructure, test release, manufacturing process development and yield enhancement, process/ product qualification and release to volume production with target performance/cost/quality. Yuri received Bachelor and Master of Science degree in Electrical Engineering from Technion Israel Institute of Technology, Haifa, Israel.

Zoe Bio:
Zoe, currently senior manager of DFT and Test in the Component Quality and Technology group at Cisco Systems, has spent much time working on component quality from ATE level testing to subsequent system level performance. Cisco’s diverse technology portfolio provides perfect insights to component DFT, test, and test gaps occurring across the supply chain. Prior to Cisco, Zoe has held various managerial and leadership roles at Procket Networks, Agilent Technologies, Hewlett Packard and Wolfson Microelectronics. She holds a B. Sc. (Hons) and Ph. D. in Electronics and Electrical Engineering from the University of Edinburgh.

Besides the throughput, the die sorting process’ main objective is to do an as thorough inspection of the devices (after dicing) as possible. This includes all six sides of the device, but also when possible the inspection into the device with infrared inspection. The requirements are for flip but also non-flip applications, and it needs to be done with th fastest throughput possible.

Gerald Steinwasser is the General Manager of Mühlbauer, Inc., a subsidiary of German Mühlbauer GmbH Co. KG. Gerald has been with the company for more than twenty years and has been focusing mainly on the bare die applications related to RFID-production, high-speed flip chip die sorting and reel-to-reel multi-component application.

Prior to Mühlbauer, Gerald has been already working in the US for a medical company, Gambro Healthcare, where he was responsible for the 24/7 production of a highly automated injection molding department. Originally from Germany, Gerald came to the US the first time in 1988 through an exchange program with the German military. Gerald graduated from the University of the German Armed Forces in Munich with a degree in aircraft & aerospace technology.